Satisfying timing constraints and resolving timing violations can be more complex for implementing circuit designs on multi-die electronic devices as compared to implementing designs on monolithic dice. In a multi-die device, multiple semiconductor die can be mounted on and interconnected through a silicon interposer. In some devices, the semiconductor dice can be nearly identical instances of a particular die. Exemplary devices include the ZYNQ® UltraScale+™ family of devices from XILINX, Inc.
In some multi-die devices, each die has multiple columns of programmable logic and interconnect circuitry, and each column can have multiple clock regions. The clock skew of a path can increase with increasing distances of launching and latching flip-flops from the clock driver of a clock region. Also, paths having latching flip-flops at the edge of a die can have the worst hold violations.
For a monolithic semiconductor die, it may be assumed that the flip-flops and signal wires are from the same process and temperature corner, and the range between the minimum and maximum delays is what one expects to see at the same corner. In multi-die devices, each die may result from a different process corner, causing a significant increase in clock skew between launching and latching flip-flops. Though the delay between flip-flops disposed in different dice is greater than the delay between neighboring flip-flops in the same die, significantly more hold violations can occur if flip-flops are placed in neighboring dice than in the same die, because the hold slack depends on the location of the connection between the dice. That is, if the dice are arranged side-by-side, and inter-die signal lines extend in a y-dimension of the stack, the hold slack of a path at one location on the x-dimension of the dice can vary significantly from the slack of a path distant from that location in the x-dimension.